Assume the following operation times for different MIPS datapath components: Instruction memory: 400 PS, Data memory: 400 PS, ALU: 300 ps, Read or Write to Register File: 200 PS Assume the following instruction mix: 30% ALU, 30% Loads, 20% stores, 20% branches. The maximum frequency at which a Single Cycle design would run at is nearly O 1300 MHZ 667 MHz 1500 MHz O 770 MHz The maximum frequency at which a Multicycle design would run at is nearly O 3.3 GHz O 1.3 GHz O 2.5 GHz O 5.0 GHz The average CPI of the multi-cycle MIPS is about 4.3 O 4.0 4.1 O 3.8