:Assume the following operation times for different MIPS datapath components Instruction memory: $400$ ps$,$ Data memory: $400$ ps$,$ ALU: $300$ ps$,$ Read or Write to Register File: $200$ ps Assume the following instruction mix: $30\%$ ALU, $30\%$ Loads, $20\%$ stores, $20\%$ branches The maximum frequency at which a Single Cycle design would run at is nearly

$MHz1300$

$MHz770$

$MHz1500$

$MHz667$

The maximum frequency at which a Multicycle design would run at is nearly

$GHz1\mathrm{.}3$

GHz $3\mathrm{.}3$

$GHz2\mathrm{.}5$

$GHz5\mathrm{.}0$

The time it takes to complete the execution of a store operation in Multicycle design is about

ps $1300$