Assume the following operation times for different MIPS datapath components:

Instruction memory: $400$ ps$,$ Data memory: $400$ ps$,$ ALU: $300$ ps$,$ Read or Write to Register File: $200$ ps Assume the following instruction mix: $30\%$ ALU, $30\%$ Loads, $20\%$ stores, $20\%$ branches.

The maximum frequency at which a Single Cycle design would run at is nearly

$1300MHz$

$770MHz$

$1500MHz$

$667MHz$

The maximum frequency at which a Multicycle design would run at is nearly

$2\mathrm{.}5CHz$

$1\mathrm{.}3GHz$

$5\mathrm{.}0CHz$

$3\mathrm{.}3GHz$

The time it takes to complete the execution of a store operation in Multicycle design is about

$1500$ ps

$1100$ ps

$1200$ ps