Assume the following operation times for different MIPS datapath componentsInstruction memory: $400$ ps$,$ Data memory: $400$ ps$,$ ALU: $300$ ps$,$ Read or Write to Register File: $200$ psAssume the following instruction mix: $30\%$ ALU, $30\%$ Loads, $20\%$ stores, $20\%$ branchesThe maximum frequency at which a Single Cycle design would run at is nearlyMHZ $6670$MHZ $1500$ @MHZ $13000$MHZ $770$The maximum frequency at which a Multicycle design would run at is nearlyCHZ $2\mathrm{.}5$ CCHZ $3\mathrm{.}3$ O GH $5\mathrm{.}0$ GHZ $1\mathrm{.}3$The time it takes to complete the execution of a store operation in Multicycle design is about