Assume the following sequence of instructions, and assume that it is executed on LEGv8 CPU (5-stages pipeline): ADD X5,X2,X1 LDUR X3,[X5,#4] LDUR X2,[X5,#0] AND X3,X5,X3 STUR X3,[X5,#0] - If there is no forwarding or hazard detection, insert NOPs to ensure correct execution. - Can you add rearrange the code to minimize the number of NOPs needed? You can assume register X7 can be used to hold temporary values in your modified code. - If the processor has forwarding, but we forgot to implement the hazard detection unit, what happens when the original code executes?