Assume using a simple in-order IF-ID-EX-MEM-WB pipeline MIPS processor. Show if there are any data hazard and stall. In the case of a data hazard, what forwarding path is activated? Circle the register(s) that cause the hazard Example ADD T8. r8. ADD r7, r6r4) Answer Data hazard No stall 1. iii.Forward WB to EXE a) ADD 17. 19. r10 SW r10, 4(17) LW 17, 4(19) b) SW r4. 4(r6) LW 13. 8(r4) c) LWr4. 8(15) SW r4, 4(T3) ADD 15. r3. r2 d) LW r4. 8(15) ADD 17. 15. r4 ADD r5. r8, r5 e) SUB 13. r3. 1 ADD T0, r0. 4 ADD r1.r0.t3