Assume you are a design engineer and are asked to design a circuit that takes as input a serial bit steam (read the input data at the rising edge of the clock signal) and outputs a 1 whenever the sequence 1011 occurs. This circuit should also have an asynchronous reset signal. Therefore, your input signals should include data_in, clk, reset and your output signal(s) should include data_out.

For instance, the following gives an example of input and outputs: data_in: 0110111011010110010110 data_out: 0000010001000010000010 (1) Draw both the Mealy and Moore type state transition diagrams (2) Write VHDL code to implement your Mealy design