Assume you have a cache with 32K blocks and each block contains 4 words and a 32-bit byte address: What is the total number of tag bits for a 4-way set associative cache ? Select one: O a. 448Kbits O b. 480Kbits O c. 416Kbits O d. 384Kbits O e, none of the options Assume you have a cache with 8K blocks and each block contains 16-words and a 64-bit byte address: What is the total number of tag bits for a Fully Associative associative cache? Select one: O a. 466944 bits O b. 516096 bits O c. 385024 bits O d. 458752 bits Oe. None of the options Consider a memory system that is composed of one cache and a main memory. The access to the main memory takes 38 ns. Given a clock frequency of 3 GHz, an instruction miss rate of 8%, and data instruction miss rate related to load and store instruction is 12%. Assume that the base CPI of 1 and that the percentage of instructions related to Store and Load is 31%. Calculate the total miss penalty in clock cycles. Answers are displayed to the nearest 2 decimal. Select one: O a. 114.00 cycles Ob. 1266.67 cycles O c. none of the options O d. 33.33 cycles