7. Assume you have a direct mapped cache with 8-rows. Now a sequence of memory addresses appears from CPU to lookup in cache. Show how the data, tag, valid bit changes with that memory address sequence. Also find out the number of hit and miss for those sequence. Show which memory addresses are hit/miss. Assume offset bits were not sent to cache for lookup.

Memory addresses (in bits)

0010000

0100001

0111010

0010000

0100000

0111010

0010000

1111111

0111010

0010000