AutoSave {} Homework2 - Memory (1) - Compatibility Mode - Word Search Gill, Arshveer Kaur GA File Home Insert Design Layout References Mailings Review View Help Share Comments X Courier New 11 A A A A EL 1 AaBbCcDc AaBbCcDc AaBbC AaBbcc Aab 1 Normal 1 No Spac... Heading 1 Heading 2 Title Find Replace Select Paste Dictate BI U ab X, X? ADA Sensitivity Editor Clipboard F Font Editing Voice Sensitivity Editor Paragraph Styles Question 4 For a direct-mapped cache design with 32-bit address, the following bits of the address are used to access the cache: Tag Index 9-4 Byte offset 3-0 31-10 a) What is the cache line size in bytes? b) How many entries does the cache have? c) What is the ratio between total bits required (data, tag, and valid bits) over the data storage bits? Starting from power on (empty cache), the following byte-addressed cache references are recorded: Address #1> 0 Address #2> 4 Address 3 16 Address #4> 132 Address #5> 232 Address za #6> 160 Address #7> 1024 Address #8> 30 Address #9> 140 Address #10> 3100 Address #11> 180 Address #12> 2180 Page 3 of 5 How many blocks are replaced? e) What is the hit ratio? List the final state of the cache, with each valid entry represented as a record of . Page 3 of 5 901 words English (Canada) C Focus 80% . 1 11:59 AM Type here to search c O 0 Ca** ENG 11 2021-02-27 18