(b) A DDR3-1333 DRAM has the following timing parameters: trc = 6 cycles, tap = 6 cycles, tras = 14 cycles, trRD = 3 cycles. What is the minimum time between activating two rows in two different banks? i. 9 ns ii. 30 ns iii. 4.5 ns iv. None of the above (b) A DDR3-1333 DRAM has the following timing parameters: trc = 6 cycles, tap = 6 cycles, tras = 14 cycles, trRD = 3 cycles. What is the minimum time between activating two rows in two different banks? i. 9 ns ii. 30 ns iii. 4.5 ns iv. None of the above