(b) Consider a cache with the following parameters: N (associativity) = 2, b (block size) = 2 words, W (word size) = 32 bits, C(cache size) = 32 K words, A (address size) = 32 bits. You need consider only word addresses. Show the tag, set, block offset, and byte offset bits of the address. State how many bits are needed for each field. What is the size of all the cache tags in bits? Suppose each cache block also has a valid bit (V) and a dirty bit (D). What is the size of each cache set, including data, tag, and status bits? Show a schematic diagram of the cache using the building blocks shown here. Only design the cache for read accesses. The cache schematic must include a tag storage array, a data storage array, address comparison (hit/miss) logic, data output selection, and any other parts you feel are relevant. Note that the multiplexer and comparator blocks may be any size (n or p bits wide, respectively), but the SRAM blocks must be 16K times 4 bits