b: MiC, high pertormance: c. IC. reduce power consamptiors 23. W. CPU, Memory. VO. intereonnection d. Parallelism; high performance 15. For-a computer compenent to fead trom memory the computer the following must be true escept: a CPU a. Be connected the system bus b. AtU b. Be able to raise interrupt 6. Hhes \& Be able to produce address data at cU d. Be able to send control signal 24. The bayis instruction crice is brokent the earlier cycle 16. The use of OMA enable communication betweent and a. Processor and 1f0 b. Memery and Processor: _ and c. Wo and Memory primary goal is to: d. Menory and Cache a. Fetch and execution i increment PC value 17. QPi is best for b. Fetch and execution; instruction in the ing (1. Many spaced component; P2P c. Encoding and decoding. Instruction in the if b. Few closely compacted components; Bus d. Fetch and execution, instruction c. Many spaced component, tus d. Few closely compacted components, p29 interpertation 18. and are advantages of point to point and bus interconnection respectively a. Lower latency and higher scalability b. Hagher scatability and lower latency c. Higher scalability and higher latency d. foner statabilaty atid iower larency: 19. PCle is based oa 3. P2P 27. The hard drive inside the computer is an internal B. Eus memory: c. Hybrid a. True because it is inside the computer d. Futwark protocol. 5. True because it holds the 05 20. Which of the system bus only takes out of the CPU c. False because it connected to //0 module a. Data b. Control d False because it engages in paging c. Address d. All buses 21. Mic improves computer performante but major 28. direct access because. challenger is: a. Software using the cores b. Hardware exploiting the cores a. Variable Access time because memory celis C. Mernory sharine. d. Power consumption b. Variable access time because of positioning defay c. Foxed time latency because memory cells are not addtessed d. Similar transfer rote because of magnetism. 22. Primary component of the Von Neumann 29. Which of the cache write policiesminimizesmemory. architecture are: a. Registers, Cache, ALU, CU. writes: b. MAR,MER IOOAR, VOBR a. Write through; it updates cache and memory C. PC,tA,AC,CU