Based on the hypothetical machine of the figure below, assume we have three data operands stored at addresses A=1, B=2, and C=4, write a code to perform the following operations in order: (You can add opcodes for the * and -):

1. 2A + 3B, (assign addresses for 2 and 3, the result must be stored in C).
2. 5A-C, (assign an address for 5 the result must be stored in A)
3. Draw the memory before and after executing each of the previous operations by showing the memory addresses and contents.

0 34 15 Opcode Address (a) Instruction format 15 0 1 S Magnitude (6) Integer format Program Counter (PC) = Address of instruction Instruction Register (IR) = Instruction being executed Accumulator (AC)= Temporary storage (c) Internal CPU registers 0001 = Load AC from Memory 0010 = Store AC to Memory 0101 = Add to AC from Memory (d) Partial list of opcodes 0 34 15 Opcode Address (a) Instruction format 15 0 1 S Magnitude (6) Integer format Program Counter (PC) = Address of instruction Instruction Register (IR) = Instruction being executed Accumulator (AC)= Temporary storage (c) Internal CPU registers 0001 = Load AC from Memory 0010 = Store AC to Memory 0101 = Add to AC from Memory (d) Partial list of opcodes