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Below questions refer to a clock cycle in which the processor fetches the following instruction word: 10001110001100000000000000100000 Assume that data memory is all zeros and

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Below questions refer to a clock cycle in which the processor fetches the following instruction word: 10001110001100000000000000100000 Assume that data memory is all zeros and that the processor's registers have the following values at the beginning of the cycle in which the above instruction word is fetched: $1 $2 $9 $10 $16 $17 $18 $PC 0x55 0x11 0x1020 0x31200x 0x15 0x2000 0x16 0x5000 0x700 0x2000 $0 $8 $15 Answer the following by referring to Figure 1 and information provided in Page 10, 11 and 12: a) What is the output of the Sign-extend unit (32bits) and the Input 1 of MUX 2 (output of Jump Shift Left 2 unit (Jump address(31-0), found in top left)) for this instruction word? b) What are the values of the ALU control unit's inputs for this instruction? c) What is the new PC address after this instruction is executed? Explain the path through which this value is determined

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