Bin Cou YA 51 S1 Num 1 Y11 ins YO Y9 2.0 S2 Num2 & digital simulation Digit TypeTimelist YY TITRE 11 Y2 18 S3 Num3 YTU 21 Y12 ins JY13 YU -1 ins TES YB Y4 ins S4 ins Num 4 times insins Figure 14: Full Adder in Qucs. The digital source S4 is a dummy source to generate signal changes every Ins. S. Solve the following tasks during the lab session: T 7: Create the circuit shown in Figure 14. The digital source shall change its output every 10ns, S2 every 20ns and S3 every 40ns. The dummy signal source S4 should change every Ins. Set the duration of the simulation to 84ns T 8: Simulate the Full Adder show the signals of A, B, Cin, S and Cout in a Timing Diagram. T 9: How long do you need to wait (in ns) after a change at the inputs so that the outputs (s and Cout) are correct? Answer separately for S and Cout. Bin Cou YA 51 S1 Num 1 Y11 ins YO Y9 2.0 S2 Num2 & digital simulation Digit TypeTimelist YY TITRE 11 Y2 18 S3 Num3 YTU 21 Y12 ins JY13 YU -1 ins TES YB Y4 ins S4 ins Num 4 times insins Figure 14: Full Adder in Qucs. The digital source S4 is a dummy source to generate signal changes every Ins. S. Solve the following tasks during the lab session: T 7: Create the circuit shown in Figure 14. The digital source shall change its output every 10ns, S2 every 20ns and S3 every 40ns. The dummy signal source S4 should change every Ins. Set the duration of the simulation to 84ns T 8: Simulate the Full Adder show the signals of A, B, Cin, S and Cout in a Timing Diagram. T 9: How long do you need to wait (in ns) after a change at the inputs so that the outputs (s and Cout) are correct? Answer separately for S and Cout