timing diagram: CP 20 Q 22 CP The example follows a rigorous design process and comes up with the design as shown below: J the design of a synchronous counter using JK flip-flops, having the following atato! J K C K n J K You have to verify the correctness of the design. To do it, build the circuit in Multisim and run the simulation. Use a logic analyzer to display CP, QO, Q1, and Q2. If everything is correct, the original timing diagram should be shown.