BONUS: Memory Hierarchy and Performance (30 points) Assume you have a IGHz processor with 2 -levels of cache and DRAM main memory. The first level cache is split for instructions and data. The system does not use early restart or critical word fint ia data blocks must be completely transferred before their results are available. The memory sys Assume that there are no other delays or overheads in memory management systems. a) [10 points] What is the average memory access time (AMAT) in clock cycles for instructions