Cache Accesses: Two caches, A and B have the following specs Cache A: 8 byte, 2-way set-associative cache with 2 byte block size Cache B: 8 byte, fully associative cache with 2 byte block size It receives memory requests to the below addresses(binary) in the given order: 0000, 0110, 1001, 0001, 0101, 1111, 0011, 0100, 0000, 1010, 1110, 0111 Assumptions Both the caches are initially empty. The processor uses LRU as the replacement policy. (a) What are the number of offset, index and tag bits for Cache A and Cache B? (b) For each of the addresses, determine if it would be a cache hit or a cache miss for Cache A Do categorize if a cache miss is compulsory, conflict or capacity. Memory Address (A)Tag bits (A) Index bits (A Miss type (A) 0110 1001 0001 0101 0011 0100 1010 1110 0111 (c) For each of the addresses, determine if it would be a cache hit or a cache miss for Cache B Do categorize if a cache miss is compulsory, conflict or capacity. Memory Address (B)Tag bits (B) Index bits (B)Hit/Miss (B) Miss type (B) 0110 1001 0001 0101 0011 0100 1010 1110 0111