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Cache and Memory Model using CACTI CACTI (http://www.cs.utah.edu/-rajeev/cacti7/ is an integrated cache and me ory model for access time, cycle time, area, leakage, and dynamic

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Cache and Memory Model using CACTI CACTI (http://www.cs.utah.edu/-rajeev/cacti7/ is an integrated cache and me ory model for access time, cycle time, area, leakage, and dynamic power. You are asked to use CACTI 7 for investigating the impact of small and simple caches using a 22nm CMOS technology node. Consider a processor using 2 cache levels. Level-1 cache is a 32 KB direct mapped cache with 16B blocks used for both instructions and data. Level-2 is address up to 2GB of main memory. Assume that both of the Level-1 and Level-2 caches are single bank. i Compare the access time, energy, leakage power, and area of the caches mentioned above.(10 points) ii Investigate the impact of varying associativity for 1, 2, and 8 on the access time, energy, leakage, and area of the Level-2 cache.(10 points) Cache and Memory Model using CACTI CACTI (http://www.cs.utah.edu/-rajeev/cacti7/ is an integrated cache and me ory model for access time, cycle time, area, leakage, and dynamic power. You are asked to use CACTI 7 for investigating the impact of small and simple caches using a 22nm CMOS technology node. Consider a processor using 2 cache levels. Level-1 cache is a 32 KB direct mapped cache with 16B blocks used for both instructions and data. Level-2 is address up to 2GB of main memory. Assume that both of the Level-1 and Level-2 caches are single bank. i Compare the access time, energy, leakage power, and area of the caches mentioned above.(10 points) ii Investigate the impact of varying associativity for 1, 2, and 8 on the access time, energy, leakage, and area of the Level-2 cache.(10 points)

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