Cache memory,
Consider a processor with an architecture similar to MIPS: byte addressable, words are 4 bytes, main memory size is 4 GB For the sections A and B below consider the following memory accesses with the given memory addresses. The table shows that for a word that contains a value represented with MI is at memory location OX10F and it is accessed for a lw instruction, Memory Content MI M2 M3 M4 MS M6 M7 Used For Memory Memory instruction Address Address in Hes in Binary Iw 10F 0001 0000 1111 Sw OAF 0000 1010 1111 Iw OFO 0000 TILL 0000 Iw 05C 0000 0101 1100 Iw 10C 0001 0000 1100 sw OFC 0000 III 1100 Sw IFC 00011111 1100 A. Consider the following cache memory configuration for the above memory accesses. N-1 (direct mapped cache), block size is 4 words, number of sets is 4. a. Give the physical (main) memory address structure as it will be used to access the cache memory. Draw a simple figure and indicate the name and size of each subfield in terms of number of bits. b. Draw the structure of a block in terms of its components: V (valid bit), D' (dirty bit), Tag. Duta. Indicate the size of each field. What is the total block size in bits? What is the SRAM size in bits? What is the cache memory total data field size in bytes? e Show the final contents of the cache memory in a figure in terms of its subfield after accessing memory locations in the order given above. Give the values of tag etc. in bits, show block data contents in terms of MI. M2 etc. d. For each memory access indicate if it is a hit or miss. Give the miss type for each case. What is the hit mate? Consider a processor with an architecture similar to MIPS: byte addressable, words are 4 bytes, main memory size is 4 GB For the sections A and B below consider the following memory accesses with the given memory addresses. The table shows that for a word that contains a value represented with MI is at memory location OX10F and it is accessed for a lw instruction, Memory Content MI M2 M3 M4 MS M6 M7 Used For Memory Memory instruction Address Address in Hes in Binary Iw 10F 0001 0000 1111 Sw OAF 0000 1010 1111 Iw OFO 0000 TILL 0000 Iw 05C 0000 0101 1100 Iw 10C 0001 0000 1100 sw OFC 0000 III 1100 Sw IFC 00011111 1100 A. Consider the following cache memory configuration for the above memory accesses. N-1 (direct mapped cache), block size is 4 words, number of sets is 4. a. Give the physical (main) memory address structure as it will be used to access the cache memory. Draw a simple figure and indicate the name and size of each subfield in terms of number of bits. b. Draw the structure of a block in terms of its components: V (valid bit), D' (dirty bit), Tag. Duta. Indicate the size of each field. What is the total block size in bits? What is the SRAM size in bits? What is the cache memory total data field size in bytes? e Show the final contents of the cache memory in a figure in terms of its subfield after accessing memory locations in the order given above. Give the values of tag etc. in bits, show block data contents in terms of MI. M2 etc. d. For each memory access indicate if it is a hit or miss. Give the miss type for each case. What is the hit mate
