Caching Problems Make sure you understand the slides related to caching and all problems related to caching on the Definitions: cache e size and ock size s number of bits required to address all memory blocks r er of bits required to address all cache lines w- number of bits required to address all units within a cache line (or memory block) Direct Mapping: l J 96 m where I cache line J block number (not the address) number of cache lines The first thing to do for these kinds of problems is to calculate the values for s, r and w for the given system. For the first set of problems assume the following system configuration: Main Memory consists of 1024 bytes and the system is byte addressable The caching logic interprets the 1024 bytes of memory as a set of blocks, each of which is 4 bytes. There are 16 cache lines. Compute s, the number of bits necessary to uniquely address all memory blocks. Memory has a total of 1024 bytes divided into blocks of 4 bytes. The number of blocks is thus 2410 242 248. Given 248 blocks, s 8. Compute r, which is the number of bits needed to uniquely address each cache line. There are 16 244 cache lines and therefore r 4. Compute w, which is the number of bits required to uniquely address each byte within a given block. Block size K 4- 242 thus w 2. In direct-mapped caches, the TAG is the most significant s r bits of the address, the LINE is the next r bits, and the offset is the least significant w bits of the address. All questions count 4 points each