calculte the bne instruction cycle time based on the following information:

Instruction Type Instruction Fetch Register Read and Decode ALU Operation Data Memory Access Register Write R-format 2 ns lui lw sW bne Assume our MIPS instruction subset has latencies. 2 ns 1 ns 1 ns 1 ns 1 ns 1 ns 1 ns 1 ns 2 ns 2 ns 2 ns ns 2 ns 2 ns 2 ns 4 ns 4 ns the above instructions and If this is used to implement a single cycle system, what is the cycle time for the bne instruction? (How long would the bne take to execute?)