Can someone fix my code? I have pasted my code along with the original directions. Please paste the entire finished code when done. Thank you! $($VHDL$)$

library IEEE;

use IEEE.STD$\_$LOGIC$\_1164.$ALL;

entity signed$\_$multiplier is

Port $($

clk : in std$\_$logic; $--$ Clock signal

rst : in std$\_$logic; $--$ Reset signal

a$\_$in : in std$\_$logic$\_$vector$(7$ downto $0)$; $--$ Input A $(8-$bit signed$)$

b$\_$in : in std$\_$logic$\_$vector$(7$ downto $0)$; $--$ Input B $(8-$bit signed$)$

result$\_$out : out std$\_$logic$\_$vector$(15$ downto $0)--$ Output result $(16-$bit signed$)$

$)$;

end signed$\_$multiplier;

architecture Behavioral of signed$\_$multiplier is

signal a$\_$reg, b$\_$reg : std$\_$logic$\_$vector$(7$ downto $0)$;

signal accumulator : std$\_$logic$\_$vector$(15$ downto $0)$ :$=($others $=>\text{'}0\text{'})$;

component multiplier$\_$unit is

Port $($

a : in std$\_$logic$\_$vector$(7$ downto $0)$;

b : in std$\_$logic$\_$vector$(7$ downto $0)$;

product : out std$\_$logic$\_$vector$(15$ downto $0)$

$)$;

end component;

component accumulator$\_$unit is

Port $($

clk : in std$\_$logic;

rst : in std$\_$logic;

data$\_$in : in std$\_$logic$\_$vector$(15$ downto $0)$;

accumulator$\_$out : out std$\_$logic$\_$vector$(15$ downto $0)$

$)$;

end component;

begin

$--$ Register A and Register B

process$($clk$,$ rst$)$

begin

if rst $=\text{'}1\text{'}$ then

a$\_$reg others $=>\text{'}0\text{'})$;

b$\_$reg others $=>\text{'}0\text{'})$;

elsif rising$\_$edge$($clk$)$ then

a$\_$reg a$\_$in;

b$\_$reg b$\_$in;

end if;

end process;

$--$ Multiplier Unit

multiplier$\_$inst : multiplier$\_$unit port map$($a$\_$reg, b$\_$reg, accumulator$(15$ downto $0))$;

$--$ Accumulator Unit

accumulator$\_$inst : accumulator$\_$unit port map$($clk$,$ rst$,$ accumulator, result$\_$out$)$;

end Behavioral;

library IEEE;

use IEEE.STD$\_$LOGIC$\_1164.$ALL;

entity multiplier$\_$controller is

Port $($

clk : in std$\_$logic; $--$ Clock signal

rst : in std$\_$logic; $--$ Reset signal

start : in std$\_$logic; $--$ Start signal to initiate multiplication

done : out std$\_$logic $--$ Done signal indicating multiplication is complete

$)$;

end multiplier$\_$controller;

architecture Behavioral of multiplier$\_$controller is

type state$\_$type is $($IDLE$,$ LOAD$\_$INPUTS, MULTIPLY, ACCUMULATE$)$;

signal current$\_$state, next$\_$state : state$\_$type :$=$ IDLE;

signal start$\_$flag, done$\_$flag : std$\_$logic :$=\text{'}0\text{'}$;

begin

process$($clk$,$ rst$)$

begin

if rst $=\text{'}1\text{'}$ then

current$\_$state IDLE;

start$\_$flag ;

done$\_$flag ;

elsif rising$\_$edge$($clk$)$ then

current$\_$state next$\_$state;

start$\_$flag start;

done$\_$flag ;

end if;

end process;

process$($current$\_$state, start$\_$flag$)$

begin

case current$\_$state is

when IDLE $=>$

if start$\_$flag $=\text{'}1\text{'}$ then

next$\_$state LOAD$\_$INPUTS;

else

next$\_$state IDLE;

end if;

when LOAD$\_$INPUTS $=>$

$--$ Code to load inputs into registers

next$\_$state MULTIPLY;

when MULTIPLY $=>$

$--$ Code to trigger multiplication

next$\_$state ACCUMULATE;

when ACCUMULATE $=>$

$--$ Code to accumulate results

next$\_$state IDLE;

done$\_$flag ;

when others $=>$

next$\_$state IDLE;

end case;

end process;

done done$\_$flag;

end Behavioral;

library IEEE;

use IEEE.STD$\_$LOGIC$\_1164.$ALL;

entity multiplier$\_$top is

Port $($

clk : in std$\_$logic; $--$ Clock signal

rst : in std$\_$logic; $--$ Reset signal

start : in std$\_$logic; $--$ Start signal for multiplication

a$\_$in : in std$\_$logic$\_$vector$(7$ downto $0)$; $--$ Input A $(8-$bit signed$)$

b$\_$in : in std$\_$logic$\_$vector$(7$ downto $0)$; $--$ Input B $(8-$bit signed$)$

result$\_$out : out std$\_$logic$\_$vector$(15$ downto $0)--$ Output result $(16-$bit signed$)$

$)$;

end multiplier$\_$top;

architecture Behavioral of multiplier$\_$top is

signal done$\_$flag : std$\_$logic;

component signed$\_$multiplier is

Port $($

clk : in std$\_$logic;

rst : in std$\_$logic;

a$\_$in : in std$\_$logic$\_$vector$(7$ downto $0)$;

b$\_$in : in std$\_$logic$\_$vector$(7$ downto $0)$;

result$\_$out : out std$\_$logic$\_$vector$(15$ downto $0)$

$)$;

end component;

component multiplier$\_$controller is

Port $($

clk : in std$\_$logic;

rst : in std$\_$logic;

start : in std$\_$logic;

done : out std$\_$logic

$)$;

end component;

begin

multiplier$\_$inst : signed$\_$multiplier port map$($clk$,$ rst$,$ a$\_$in$,$ b$\_$in$,$ result$\_$out$)$;

controller$\_$inst : multiplier$\_$controller port map$($clk$,$ rst$,$ start, done$\_$flag$)$;

end Behavioral;