Can someone please explain why I am getting this error? And show how to fix the code using Xilinx (Vivado)

Sources ? OEX Project Summary x decod2_4.vhd * x testbench.vhd 0 C/Users/dcoel/Lab_4.srcs/sources_1ew/decod2_4.vhd Design Sources (2) Syntax Error Files (1) ) decod24.vhd decod2_4_vhd Behavioral) (decod2_4.vhid) > Constraints Simulation Sources (3) sim_1(3) > Syntax Error Files (2) () > testbench(Behavioral) (testbench vhd) (1) > Utility Sources Hierarchy Libraries Compile Order a X X 120 1 2 3 4 library IEEE: 5 use IEEE. STD_LOGIC_1164.ALL; 6 use IEEE.STD LOGIC ARITH. ALL: 7 use IEEE. STD_LOGIC_UNSIGNED. ALL; 8 -- Uncomment the folloving library declaration if using 10 -- arithmetic functions with Signed or Unsigned values 11 use IEEE.NUMERIC STD.ALL: 12 13 d -- Uncomment the following library declaration if instantiating -- any Xilinx lear cells in this code. 15 --library UNISIM: 16 --tase UNISIM. VComponents.all; 17 18 entity decod2_4_vhd is 19 Port (A in STD LOGIC: 20 B : in STD_LOGIC ; 21 00: out STD LOGIC; 22 01 : out STD LOGIC; 23 02: out STD LOGIC; 24 03 : out STD_LOGIC; 25 00 Out STD LOGIC: 26 01 out STD LOGIC; 27 02 : Out STD LOGIC: 20 03 out STD LOGIC): 29 end decod2_4_vhd: 30 31 architecture Behavioral of decod2_4_vhd is 32 33 begin 34 35 00 HDL 9-806] Syntax error near "00" (decod2_4.vhd:22] (6 more like this) Sources ? OEX Project Summary x decod2_4.vhd * x testbench.vhd 0 C/Users/dcoel/Lab_4.srcs/sources_1ew/decod2_4.vhd Design Sources (2) Syntax Error Files (1) ) decod24.vhd decod2_4_vhd Behavioral) (decod2_4.vhid) > Constraints Simulation Sources (3) sim_1(3) > Syntax Error Files (2) () > testbench(Behavioral) (testbench vhd) (1) > Utility Sources Hierarchy Libraries Compile Order a X X 120 1 2 3 4 library IEEE: 5 use IEEE. STD_LOGIC_1164.ALL; 6 use IEEE.STD LOGIC ARITH. ALL: 7 use IEEE. STD_LOGIC_UNSIGNED. ALL; 8 -- Uncomment the folloving library declaration if using 10 -- arithmetic functions with Signed or Unsigned values 11 use IEEE.NUMERIC STD.ALL: 12 13 d -- Uncomment the following library declaration if instantiating -- any Xilinx lear cells in this code. 15 --library UNISIM: 16 --tase UNISIM. VComponents.all; 17 18 entity decod2_4_vhd is 19 Port (A in STD LOGIC: 20 B : in STD_LOGIC ; 21 00: out STD LOGIC; 22 01 : out STD LOGIC; 23 02: out STD LOGIC; 24 03 : out STD_LOGIC; 25 00 Out STD LOGIC: 26 01 out STD LOGIC; 27 02 : Out STD LOGIC: 20 03 out STD LOGIC): 29 end decod2_4_vhd: 30 31 architecture Behavioral of decod2_4_vhd is 32 33 begin 34 35 00 HDL 9-806] Syntax error near "00" (decod2_4.vhd:22] (6 more like this)