Question
Can you answer these 5 MCQs? 1) Jump and Jump and Link instructions have a six-bit op-code and a 26-bit jump address field. How is
Can you answer these 5 MCQs?
1) Jump and Jump and Link instructions have a six-bit op-code and a 26-bit jump address field. How is the full 32-bit Jump Address calculated? a. The jump address field is sign-extended six bits to the left. b. The leftmost four bits of the PC are concatenated with the jump address field, and two bits of zero are concatenated to the end of that. c. The leftmost six bits of the PC are concatenated with the jump address field. d. The jump address is ANDed with Register 0 to produce the jump address 2) How is a branch target address calculated? a. Sign-extend bits 15:0 of the instruction, append two bits of zeros, and add the result to the PC. b. Zero extend bits 15:0 of the instruction, append two bits of ones, and subtract the result from the PC. c. Add the immediate operand to register zero, and sign extend the result. d. Concatenate the leftmost 16 bits of the PC with the rightmost 16 bits of the instruction. 3) What arithemetic operation is performed by the ALU for branch instructions? a. The ALU is not used for branch instructions. b. The ALU subtracts one register operand from the other one to see if they are different. c. The ALU adds the branch target address to the link register. d. The ALU performs the SLT function to determine the branch target address. 4) What is the name for the problem in a pipeline design when an instruction needs the result of a previous instruction to use as an operand, but that result has not been written back into the register file yet? a. The register write delay loop problem b. Control hazard c. Data hazard d. Syntax error 5) How is the effective address calculated for lw and sw instructions? a. By converting the byte address to a word address and adding it to the PC. b. By putting the immediate operand into register 0. c. By sign-extending bits 15:0 of the instruction, and adding that to the contents of the register whose number is in bits 25:21 of the instruction. d. By using the shamt field of the instruction to determine where to branch.
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