Can you help me to answer these questions please. We wrote a verilog code on Vivado

I will attach the codes we used

`timescale 1ns / 1ps

module main(a, b, c, d, e);

input a, b, c;

output reg d;

output reg e;

always @ (a , b , c)

if (c == 0)

begin

d = a&b;

e = a | b;

end

else

begin

d = a | b;

e = a & b;

end

endmodule

# inputs

set_property PACKAGE_PIN R2 [get_ports a]

set_property IOSTANDARD LVCMOS33 [get_ports a]

set_property PACKAGE_PIN T1 [get_ports b]

set_property IOSTANDARD LVCMOS33 [get_ports b]

set_property PACKAGE_PIN U1 [get_ports c]

set_property IOSTANDARD LVCMOS33 [get_ports c]

# outputs

set_property PACKAGE_PIN L1 [get_ports d]

set_property IOSTANDARD LVCMOS33 [get_ports d]

set_property PACKAGE_PIN P1 [get_ports e]

set_property IOSTANDARD LVCMOS33 [get_ports e]

`timescale 1ns / 1ps

// After running the simulation, if you do not see "Testbench Complete"

// on the console, then increase simulation time to say 10000 ns

// define a new module to test your main module

module tb_main ();

reg A, B, C; // declare inputs in your main module as registers

wire D, E; // declare outputs in your main module as wires

// input, output declarations have been deliberately made different

// from those of "main". They could have been the same, however

// Instantiate the unit under test (uut), here main

main uut (A, B, C, D, E);

// Parameters could have been written as

// .a(A), .b(B), etc to indicate the correspondence of

// local variable "A" with the main parameter "a".

// With this correspondence, the order of parameters in the instantiation

// and the module definition need not be the same. For example we could

// write main uut (.a(A), .c(C), .e(E), .b(B), .d(D))

// initialize inputs

initial

begin

$display ("Testbench start");

$display ("a b c | d e");

{A,B,C} = 0; // concatenate A, B, C together and initialize to 0

end

// Repeated Execution block

always

begin

#10; // wait for 10 ns

$display ("%d %d %d | %d %d", A, B, C, D, E);

// displays the current value of {A,B,C} and D, E

if ({A,B,C} == 'b111) // 'b111 indicates 111 in binary

begin

$display ("Testbench end");

$finish;

end

else

{A,B,C} = {A,B,C} + 1;

end

endmodule

(b) Why is it necessary for you to specify the part number etc. when to specify your project (see page 2 of the Vivado note)? (c) Why is it necessary for you to provide details in the constraints file (even though you have defined the module in the Verilog file). (d) What parallel do you see between programming the Basys3 board and implementing a circuit on the Trainer kit? What differences do you see? (e) Why is it important to use a testbench? (f) What difference did the change of {A,B,C} to {C,A,B} in the testbench make and why? (g) What difference did the "if statement change" in the testbench make and why