can you help me to solve question 4.1 and 4.2

3.1 (1pts) Draw a diagram showing a two-input NAND constructed fre 3.2 (1pts) For the 1-bit memory below, if the control is 0, the input is 1 will the new output be? Data In Out Ctrl Feedback Figure C.5: Simple Memory Device 4.1 (1pts) Draw the diagram of a S-R latch. 4.2 (1 pts) Draw the diagram for a Half-Adder. 5. (2pts) Memory Design Problem: Problem Specifications: Ram ch needs 2M addresses of 16 bits per address As usual, need V+, GND, the best organization. Explain/justify your answer and show all you diagram of your solution