Can you please answer (b) (c) (d) please

(a) Assume the usage of 5-stage instruction pipelining (Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Memory (MEM), Write Back (WB) with a program consisting of 1000 instructions. Assume that clock cycle per instruction is 1 time unit. Answer the following: i) Assume the usage of ideal pipelining without any hazards, how many time units will be needed to complete all the 1000 instructions. (1 mark) ii) If pipelining is not used, how many time units will be required to execute these 1000 instructions (1 mark) iii) What is the speedup factor on the usage of pipelining for these 1000 instructions. (1 mark) (b) Identify the type of data hazard possible in the following instructions in a hypothetical computer and explain the reason. ADD R2,RI,R3 SUB R4, R2,R4 (2 marks) () Assume that the following instruction has to be executed in a hypothetical computer. SUB RI, [X] X is a indirect memory address which contains the address of data. This instruction is available in memory location Y. Identify the microoperations required to execute this instruction, involving fetch cycle. indirect cycle and execute cycle. (3 marks) (d) Assume that in a multiprocessing environment, data X is available in main memory. If this data is brought into local cache memory of three processors (P1,P2, P3), briefly explain how the cache coherence problem can occur with an illustration (2 marks)