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Can you please construct testbench for this?(and can you fix this code if its wrong) If you can also create a circuit and attach a
Can you please construct testbench for this?(and can you fix this code if its wrong) If you can also create a circuit and attach a screenshot that'll be a big thumbs up. I know I asked a lot but, whatever you do I'll still appreciate it:) module alu( input [3:0] a, input [3:0] b, input [3:0] opcode, output [3:0] result, output carry, output zero ); reg [3:0] result; reg carry; reg zero; always @* begin case (opcode) 4'b0000: result = a & b; // logical AND 4'b0001: result = a | b; // logical OR 4'b0010: result = a ^ b; // logical XOR 4'b0011: result = ~(a | b); // logical NAND 4'b0100: result = a + b; // addition 4'b0101: result = a - b; // subtraction 4'b0110: result = a 4'b0111: result = a >> b[0]; // logical shift right 4'b1000: result = (a == b) ? 4'b0001 : 4'b0000; // equal comparison 4'b1001: result = (a > b) ? 4'b0001 : 4'b0000; // greater comparison 4'b1010: result = (a * b); // multiplication 4'b1011: result = (a / b); // division 4'b1100: result = {a[3],a[2],a[1],a[0]}; // rotate left 4'b1101: result = {a[1],a[2],a[3],a[0]}; // rotate right 4'b1110: result = ~(a ^ b); // logical XNOR 4'b1111: result = ~(a & b); // logical NOR default: result = 4'bxxxx; // invalid opcode endcase end // Assign the result and zero flag outputs assign result = temp; assign zero = (temp == 0); endmodule Task 1 (20 points) By using Verilog language construct 4-bit Arithmetic and Logic Unit (ALU) which will be able to execute the following instructions: Logical NOR, Logical shift left, Logical shift right, Logical xor, Multiplication, Logical NAND, Subtraction, Addition, Equal comparison, Rotate right, Division, Logical XNOR, Rotate left, Greater comparison, Logical OR, Logical AND. Task 2 (20 points) Construct testbench for circuit from task 1 by using Verilog language and then create appropriate circuit
Can you please construct testbench for this?(and can you fix this code if its wrong) If you can also create a circuit and attach a screenshot that'll be a big thumbs up. I know I asked a lot but, whatever you do I'll still appreciate it:)
module alu(
input [3:0] a,
input [3:0] b,
input [3:0] opcode,
output [3:0] result,
output carry,
output zero
);
reg [3:0] result;
reg carry;
reg zero;
always @* begin
case (opcode)
4'b0000: result = a & b; // logical AND
4'b0001: result = a | b; // logical OR
4'b0010: result = a ^ b; // logical XOR
4'b0011: result = ~(a | b); // logical NAND
4'b0100: result = a + b; // addition
4'b0101: result = a - b; // subtraction
4'b0110: result = a
4'b0111: result = a >> b[0]; // logical shift right
4'b1000: result = (a == b) ? 4'b0001 : 4'b0000; // equal comparison
4'b1001: result = (a > b) ? 4'b0001 : 4'b0000; // greater comparison
4'b1010: result = (a * b); // multiplication
4'b1011: result = (a / b); // division
4'b1100: result = {a[3],a[2],a[1],a[0]}; // rotate left
4'b1101: result = {a[1],a[2],a[3],a[0]}; // rotate right
4'b1110: result = ~(a ^ b); // logical XNOR
4'b1111: result = ~(a & b); // logical NOR
default: result = 4'bxxxx; // invalid opcode
endcase
end
// Assign the result and zero flag outputs
assign result = temp;
assign zero = (temp == 0);
endmodule
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