Can you provide some explanation also, please? Thank you so much

Instruction This is a three-part question about critical path calculation. Consider a simple single-cycle implementation of LEGv8 ISA. The operation times for the major functional components for this machine are as follows: 90 ps 70 ps 30 ps 20 ps 50 ps 20 ps ALU Add ALU Control Unit Shifter Control Unit/ROM Sign/zero extender 2-1 MUX Memory (read/write) (instruction or data) PC Register (read action) PC Register (write action) Register file (read action) Register file (write action) Logic (1 or more levels of gates) 20 ps 140 ps 20 ps 20 ps 80 ps 60 ps 10 ps Below is a copy of the LEGV8 single-cycle data path design. In this implementation the clock cycle is determined by the longest possible path in the machine. The critical paths for the different instruction types that need to be considered are: R-format, Load-word, and store-word. A ALU result Adil Shift left PCSIC Instruction (31-26 () J | Regost Branch Merad Merite Control Mom ALUS RegWrite Top Instruction 25-211 ( Read address Instruction [20-16) LO Zero Read Read Read data 1 register 2 Registrs Read Witte data 2 register Witte data A ALU result Address Read data Instruction memory w Instruction (15-111 Data memory Write data Instruction 15-01 16 32 Sign extend ALU control Instruction 15-01 [33 points] (Question 1 Part A) In the table below, indicate the components that determine the critical path for the respective instruction, in the order that the critical path occurs. If a component is used, but not part of the critical path of the instruction (i.e. happens in parallel with another component), it should not be in the table. The register file is used for reading and for writing; it will appear twice for some instructions. All instructions begin by reading the PC register with a latency of 20ps. Hardware Elements Used By Instruction Instruction Type R-Format D-Format Load D-Format Store i-Format B-format CB-format Instruction This is a three-part question about critical path calculation. Consider a simple single-cycle implementation of LEGv8 ISA. The operation times for the major functional components for this machine are as follows: 90 ps 70 ps 30 ps 20 ps 50 ps 20 ps ALU Add ALU Control Unit Shifter Control Unit/ROM Sign/zero extender 2-1 MUX Memory (read/write) (instruction or data) PC Register (read action) PC Register (write action) Register file (read action) Register file (write action) Logic (1 or more levels of gates) 20 ps 140 ps 20 ps 20 ps 80 ps 60 ps 10 ps Below is a copy of the LEGV8 single-cycle data path design. In this implementation the clock cycle is determined by the longest possible path in the machine. The critical paths for the different instruction types that need to be considered are: R-format, Load-word, and store-word. A ALU result Adil Shift left PCSIC Instruction (31-26 () J | Regost Branch Merad Merite Control Mom ALUS RegWrite Top Instruction 25-211 ( Read address Instruction [20-16) LO Zero Read Read Read data 1 register 2 Registrs Read Witte data 2 register Witte data A ALU result Address Read data Instruction memory w Instruction (15-111 Data memory Write data Instruction 15-01 16 32 Sign extend ALU control Instruction 15-01 [33 points] (Question 1 Part A) In the table below, indicate the components that determine the critical path for the respective instruction, in the order that the critical path occurs. If a component is used, but not part of the critical path of the instruction (i.e. happens in parallel with another component), it should not be in the table. The register file is used for reading and for writing; it will appear twice for some instructions. All instructions begin by reading the PC register with a latency of 20ps. Hardware Elements Used By Instruction Instruction Type R-Format D-Format Load D-Format Store i-Format B-format CB-format