Can you solve questions 1,2 and 3?

Q1: For the following datapath and control design: (a) Why the PC register is increased by 4 not 1 ? (b) What is the two possible addresses that can be stored in the PC register if the value of BR is equal to 1 ? (c) Determine the value of control signals if we want to execute lw instruction. Q2: Consider a non-overlapped memory system that has two levels of memories. The cache memory has an access time of 100ns and the RAM memory has an access time of 1200ns. (a) If the effective access time is 50% greater than the cache access time. What is the hit ratio H ? (b) Suppose that we can change the cache design such that we get H equals to 0.9916 . Calculate the new effective access time and determine if this change improves the performance or not? Part II: Answer only one question (Section-Based): Section A: Q3: Assume that we have a cache memory consists of 64 lines and a main memory (RAM) contains 2K blocks of 128 words each. Show the format of addresses generated by CPU for the following: (a) If the cache memory uses the direct mapping. (b) If the cache memory uses the associative mapping. (c) If the cache memory uses 4-way set associative mapping