can you use d flipflop to create not if else statements

dff code:

// FPGA projects using Verilog/ VHDL // fpga4student.com // Verilog code for D Flip FLop // Verilog code for rising edge D flip flop module RisingEdge_DFlipFlop(D,clk,Q); input D; // Data input input clk; // clock input output Q; // output Q always @(posedge clk) begin Q   5.2.3 4-Bit Synchronous Parallel Load Shift Register with Counter and Asynchronous Reset: Write a Verilog code to read an 8-bit message from parallel input (user switches) into a shift-register, and use the shift function together with a counter to determine the number of '1's in the message (Don't use behavioral design instead used flip-flops) (no need for designing the 7-segment LED decoder here, the decoder will be used during the experimental work.) rst Data[7:01 Q17:0) Paralle-In Shift Register Ones (3:0) cik load (a) rst 1 0 load X  1 0 en  0 1 1 (b) Q[7:0) 0 0 Data Data Ones(3:0) 0 0 0 #ones 0 0