Can you write testbench too?

The aim of the pulse width modulation (PWM) is forming a digital signal with constant period but with varying on and off time values within a period. Form a Verilog description that the constant period of the PWM is 10 times the input clock period. (Clock frequency is divided by 10) On and off time values will be selected by the user. For instance, if the user enters 3 , PWM signal is ' 1 ' for three steps and ' 0 ' for seven steps in the period