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CCPS 5 9 0 Lab 1 Instruction cycle, memory hierarchy, signals Preamble This lab has two parts to it . The first involves problem solving
CCPS Lab
Instruction cycle, memory hierarchy, signals
Preamble
This lab has two parts to it The first involves problem solving and can be completed on paper or digitally In either case, make sure your writing is LEGIBLE. If I can't read it I can't mark it The second part involves writing programs that send and catch signals.
Lab Description Part I
Consider the hypothetical processor with instruction format seen below:
tableOpcodeAddress,
In class, we saw an example that considered three instruction opcodes. For this question, we add two more for a total of five. They full set of opcodes, in binary, is as follows:
Load AC from memory
Load AC from device
Store AC to memory
Store to device
Add to AC from memory
For the new opcodes and the address field in the instruction refers to some external IO device. Show the execution for a program that does the following:
Load AC from device address
Add contents of memory location
Store AC to device address
In your answer, it is enough to show the contents of the registers at each step. The initial state of the CPU, in the same format we saw in class, can be seen in the first fetch stage on the next page. You must fill in the memory and register values for this initial fetch stage and all remaining instruction cycles. Use Hexadecimal digits when filling in the stages.
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