CCPS$590$ Lab $1$

Instruction cycle, memory hierarchy, signals

Preamble

This lab has two parts to it$.$ The first involves problem solving and can be completed on paper $($or digitally$).$ In either case, make sure your writing is LEGIBLE. If I can't read it$,$ I can't mark it$.$ The second part involves writing $C$ programs that send and catch signals.

Lab Description $-$ Part I

Consider the hypothetical processor with instruction format seen below:

$\backslash$table$[[,34,15],[$Opcode$,$Address,$]]$

In class, we saw an example that considered three instruction opcodes. For this question, we add two more for a total of five. They full set of opcodes, in binary, is as follows:

$0001=$ Load AC from memory

$0011=$ Load AC from $\frac{1}{0}$ device

$0010=$ Store AC to memory

$0111=$ Store $AC$ to $\frac{\text{I}}{O}$ device

$0101=$ Add to AC from memory

For the new opcodes $0011$ and $0111,$ the address field in the instruction refers to some external I$/$O device. Show the execution for a program that does the following:

Load AC from device $5($address $705).$

Add contents of memory location $305.$

Store AC to device $6($address $706).$

In your answer, it is enough to show the contents of the registers at each step. The initial state of the CPU, in the same format we saw in class, can be seen in the first fetch stage on the next page. You must fill in the memory and register values for this initial fetch stage and all remaining instruction cycles. Use Hexadecimal digits when filling in the stages.