Clock frequency (F) and clock time-period (t) of a clock are related by the expression t1/F. A designer, who is servicing a client decides to clock his circuit at 100 MHz (1 MHz-10 Hz). The circuit contains a D F/F based section which feeds to a register block and receives an output from the block to D (see figure below). The propagation delay in the D F/F is 3 ns and register block has a propagation delay of 4 ns 6. Register block D Q (b) A new specification requires that a NOT-gate be added between register-block output and D- gate input. Propagation delay in the new NOT-gate is 2 ns. Identify if the such a design would function as expected