CMP 334 Exam 2 (Spring 2018) 1) Write a subprogram (in RISC common assembly language) that takes three values in registers $A, $B, and $C and returns in register $F the following result: 1 if $A = $B = $C 2 if $A = $B ? $C or $B = $C ? $A or $C = $A ? $B 3 if $A ? $B ? $C ? $A Your subprogram may use any of the registers $0 $F, but it should not load from, or store to, main memory. Here is a possible driver for the subprogram: sys read, $A sys read, $B sys read, $C bl $E, 0x4800 sys print, $F sys end 2) Fill in the transition truth table for the following circuit. (You may assume that Yold = Xold.) A B Xold Xnew 0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 0 1 1 1 0 B X Y A For the following questions assume the following distribution of instructions 50% ALU instructions 20% Load instructions 05% Store instructions 20% Conditional branch instructions 05% Unconditional branch instructions 3) On average, how many memory accesses are required for each instruction. 4) On a multi-cycle per instruction processor: ALU instructions require 5 cycles; loads, 9 cycles; stores, 7 cycles; taken conditional branches, 8 cycles; not taken conditional branches, 6 cycles; and unconditional branches, 4 cycles. If one fifth of all conditional branches are taken, what is the CPI for this distribution of instructions? For the next three questions the processors execute instructions in the following stages: IF 100 ps ID 100 ps EX 200 ps MEM 250 ps WB 150 ps. 5) What would be the cycle time of a single-cycle-per-instruction-execution processor having these stages? 6) What would be the cycle time of a pipeline processor with these stages? 7) What would be the speedup of the pipeline processor in #6 over the single-cycle processor of #5? 8) Compute the stall cycles per instruction due to each of the following hazards a) a 1 cycle delay for 1 of every 20 load instructions b) a 3 cycle delay for every taken conditional branch ( of conditional branches) c) a 30 cycle delay for 1 of every 250 memory accesses d) a 8,000 cycle delay for 3 of every 100,000 instructions 9) What is the CPIactual for the processor in #8 with the four indicated hazards? 10) Use Amdahl's law to compute the overall speedup for the following improvements. (Assume that the CPIactual for the unimproved machine is 1.5.) a) reduce the frequency of stalls in #8 a) form 1 in 20 to 1 in 30 b) reduce the cost of the stalls in #8 b) from 3 to 2 cycles c) reduce the cost of the stalls in #8 c) from 30 to 25 cycles d) reduce the cost of the stalls in #8 d) from 8,000 to 6,000 cycles 11) Which of the improvements in #10 is most effective (produces the greatest overall speedup)? 12) This question explores the effect of static branch prediction on a pipeline processor whose only hasards are associated with conditional branches. Recall that 20% of all instructions are conditional branches. Assume that of these branches are backward and are forward and that 13 out of 15 backward branches and 3 out of 5 forward branches are taken. All incorrectly predicted branches stall for 3 cycles. Correctly predicted taken branches stall for 2 cycles. And, correctly predicted not taken conditional branches do not stall at all. Compute the SPCI (stall cycles per instruction) for each of the following static branch prediction strategies: a) predict all branches not taken. b) predict backward branches not taken, forward branches taken. c) predict backward branches taken, forward branches not taken. d) predict all branches taken.