Complet all parts and show work! A 32-bit DLX computer transfers a 512-byte sector (128 words) from the hard disk to the main memory by using DMA. The disk reads the sector from the platter into a special memory called the disk cache which is part of the disk controller. Thereafter the data is transmitted from the disk cache to the main memory via the bus by using DMA. Compute this DMA transfer time from disk cache to main memory. The following are the parameters we know: The bus is 4 words wide and the time to propagate a signal on the bus is 4 processor cycles. (This is often called the bus cycle time.) The disk cache is 1 word wide and has an access time of 1 processor cycle. .The main memory is 16 words wide and has an access time of 80 processor cycles. Assume that main memory accessed cannot be pipelined (i.e., we must wait for the previous access to finish before the next access can be issued. The process of transfer is as follows. First, four words are read from the disk cache into hardware registers. When done, they are sent together on the bus in one transfer. When four successive bus transfers are received at the memory, they are written together to the memory. Different stages in this process are overlapped (pipelined) to the extent possible - carefully think through what can be overlapped Complet all parts and show work! A 32-bit DLX computer transfers a 512-byte sector (128 words) from the hard disk to the main memory by using DMA. The disk reads the sector from the platter into a special memory called the disk cache which is part of the disk controller. Thereafter the data is transmitted from the disk cache to the main memory via the bus by using DMA. Compute this DMA transfer time from disk cache to main memory. The following are the parameters we know: The bus is 4 words wide and the time to propagate a signal on the bus is 4 processor cycles. (This is often called the bus cycle time.) The disk cache is 1 word wide and has an access time of 1 processor cycle. .The main memory is 16 words wide and has an access time of 80 processor cycles. Assume that main memory accessed cannot be pipelined (i.e., we must wait for the previous access to finish before the next access can be issued. The process of transfer is as follows. First, four words are read from the disk cache into hardware registers. When done, they are sent together on the bus in one transfer. When four successive bus transfers are received at the memory, they are written together to the memory. Different stages in this process are overlapped (pipelined) to the extent possible - carefully think through what can be overlapped