Complete the following peice of VHDL code with the necessary VHDL statements for a counter that counts through this sequence(0,24,30,9,3,21) repeatedly library IEEE; use IEEE.STD LOGIC_1164.ALL; entity GCC is Port (systemClock, reset : in STD_LOGIC; end GCC; architecture Behavioral of GCC is stateOutput: out STD_LOGIC_VECTOR (4 downto 0); component Freq Divider is Port (systemClock: in STD LOGIC; slowClock: out STD_LOGIC); end component signal nextState, presentState: std_logic_vector(5 downto 0)- "00000"; signal slowClock: std_logic; begin FD0: FreqDivider port map (systemClock-> systemClock, slowClock-> slowClock); process (slowClock, reset) begin if (reset = '1 ') then presentState end Behavioral Points 2.0