Complete the following to have the correct answer: 1. What will be the final value of x1and w1 for the following different Verilog codes, if the initial values of x1 and y equal 1, 5 respectively.

A. always @ (posedge clk) begin x1 = y; w1 = x1 + 2; end

X1 =____, W1 =_____,

2. What do this code do? module p ( a, b, r, w) input a, b; output r, w; assign r= a ^ b; assign w= a & b; end endmodule

3. what is the value of sum , count?

while(count<10) begin sum=sum+5; count=count+1; end

4. What does the following code do always @ (posedge clock) begin a <= b; b <= a; end

a) Shift a by b times b) Swap the content of a and b c) Shift b by a times d) Check if a equals b

5. correct the error in the Verilog . # 4-bit Adder subtractur module addSub(A, B, sel ; Result); input sel; input [5:0] A,B; output [3:0] Result; wire [3:0] result; assign Result = (sel)? A + B : A - B; endmodul