Complete the following Verilog Module for a behavioural 6-bit Adder/Subtractor:

module add_sub_6(output i6_t result, input i6_t a, b, input logic add_sub ); endmodule

Test Bench:

typedef logic signed [5:0] i6_t; module main; i6_t a, b, result; logic pass_fail, add_sub; task check_add_sub( string op ); begin i6_t r; a = -32; repeat( 64 ) begin b = -32; repeat( 64 ) begin #10; r = add_sub ? a+b : a-b; if ( result !== r ) begin if ( pass_fail ) begin $display("first mismatch %1d %s %1d, %b != %b", a, op, b, result, r ); $display("no more errors reported"); end pass_fail = 0; end b = b + 1; end a = a + 1; end end endtask add_sub_6 dut(result, a, b, add_sub ); initial begin pass_fail = 1; add_sub = 1; check_add_sub( "+" ); add_sub = 0; check_add_sub( "-" ); if ( pass_fail == 1 ) $display(" Test passed"); else $display(" Test failed"); end endmodule