Complete the timing diagram of the following circuit, which computes integer square root using a binary search approach. n = 12. Note that rm = 1 if > D, else 0, re = 1 if ?-D, else 0. Shift registers: serial input is 10'. The value of D is an unsigned decimal. FSM: j is an embedded counter, j changes on the clock edge FSM resetn-0 DI S1 100..0 01000...0 ? n-1 010. . .0 00010...0 2 RIGHT data_r data sqr RIGHT S2 Tk re comp [log2 2nl Er, Ei-1 next r re Ed 2rkak 2n 2. j=1 FSM sr Ei Li S3 done ? done clock resetn 10 T9 10 22n-4 218 216 214X 212210 I 22n-2I 10 T ? r | ?? ? ? ?? r . state S1 ?? ? ? ?? ? ?? ? ?? ? . done Complete the timing diagram of the following circuit, which computes integer square root using a binary search approach. n = 12. Note that rm = 1 if > D, else 0, re = 1 if ?-D, else 0. Shift registers: serial input is 10'. The value of D is an unsigned decimal. FSM: j is an embedded counter, j changes on the clock edge FSM resetn-0 DI S1 100..0 01000...0 ? n-1 010. . .0 00010...0 2 RIGHT data_r data sqr RIGHT S2 Tk re comp [log2 2nl Er, Ei-1 next r re Ed 2rkak 2n 2. j=1 FSM sr Ei Li S3 done ? done clock resetn 10 T9 10 22n-4 218 216 214X 212210 I 22n-2I 10 T ? r | ?? ? ? ?? r . state S1 ?? ? ? ?? ? ?? ? ?? ? . done