Compute transition times for a four-input NAND gate with 8/2 pulldown (the W/L = 8/2 for n-type transistors) and 8/2 pullup that drives an identically-sized NOR four-input gate (the NAND gate only drives one input of the NOR gate)
a) Rise time
b) Falltime

Please use the 180 nm process parameters. For NMOS as Rn = 6.47KΩ, for PMOS as Rp = 29.6KΩ, and Cl =0.89f F)