computer architecture

In a single-core CPU that has a five-stage pipeline, it takes 1 CPU clock cycle to fetch the instruction, 1 CPU clock cycle to decode the instruction, 2 CPU clock cycle to fetch the operands from the registers, 3 CPU clock cycles to execute the instruction, and 1 CPU clock cycles to write the result back to the register. You do not need to consider any storage other than the registers, and you should assume the instructions are executed in their original order. (1) How many CPU clock cycle does it need to execute approximately 30,000 instructions? (10%) (2) Let us assume the CPU frequency is 2.4GHz (i.e., every CPU clock cycle is 0.417 nano second). What is the performance of the machine in terms of MIPS (Million Instructions Per Second)? (5%) 1