Write a self-checking test bench for the given SystemVerilog module: module testMe (input logic j, k, m, output logic p); assign p = -j & k & m | -j& -k & m Ij& -k & -m endmodule You only need to include the code from the initial begin statement until the end of the module. Please include an assert and error statement for each possible combination. Edit View Insert Format Tools Table 12pt v Paragraph v |BIU A- 2v Tv | :