computer organization course

Consider the slx stage pipeline processor, that implements predict not taken policy for branch instructions. In this processor memory stage is divided into two stages Mem1 and Mem2. Originally, the branch condition and branch/jump target calculation was done in execute stage and forwarding an stalling hardwares were used target calculation was done in execute where needed. It is proposed to modify the pipeline, so that the branch condition and branchyjump target calculation are done in decode stage. However, the clock cycle time of the new hardware is 2% more as compared to the old one. Compare the performance of the old and the proposed pipelining hardwares Assume 56% of the branch instructions are taken. Also, assume that 40% of the load instructions are forwardable, 58% of the remaining can be forwarded after the delay of one cycle. Assume the following instruction mix: ALU-40%, Load 20%, store-os, Branch-20%. I-106 Things to think about a. Will there be extra delay in simple ALU instructions due to extra mem stage. b. Will there be extra delay in load instruction due to extra mem stage Remember: you have to calculate the execution time two times, [3,4]