Consider a 10-bit ADC with a full-scale voltage of 1 volt. Suppose it is tested in two ways. First, its input is set to mid scale, and the sampling and conversion rate are each set to 1 GHz. A histogram of digital outputs is collected and shows that only two codes occur. Second, its input is set to a 1-GHz sinusoidal signal whose amplitude is equal to the limit allowed by the full-scale range. Also, assume that the ADC sampling and conversion rate are each again set equal to 1 GHz, and the sample timing is adjusted so that the input is sampled when the input voltage is equal to mid scale on average. A histogram of digital outputs is collected in this case as well. The resulting histogram shows that 50 output codes occur, and the standard deviation of this histogram is 10 codes. Assume that the sampling rate and the conversion rate are both inside the speed range that can be comfortably handled by this ADC. What do you conclude about the ADC characteristics from these two tests? Consider a 10-bit ADC with a full-scale voltage of 1 volt. Suppose it is tested in two ways. First, its input is set to mid scale, and the sampling and conversion rate are each set to 1 GHz. A histogram of digital outputs is collected and shows that only two codes occur. Second, its input is set to a 1-GHz sinusoidal signal whose amplitude is equal to the limit allowed by the full-scale range. Also, assume that the ADC sampling and conversion rate are each again set equal to 1 GHz, and the sample timing is adjusted so that the input is sampled when the input voltage is equal to mid scale on average. A histogram of digital outputs is collected in this case as well. The resulting histogram shows that 50 output codes occur, and the standard deviation of this histogram is 10 codes. Assume that the sampling rate and the conversion rate are both inside the speed range that can be comfortably handled by this ADC. What do you conclude about the ADC characteristics from these two tests