Consider a 16-bit processor with a directly mapped cache with 16 Byte cache blocks and 4 entries

Cache Index Hit or Miss? Byte address Block address (binary) Tag (hex) (binary) 1010 00 3(112 Miss 0xA30 1010 0011 0000 1010 00 1010 00 1010 01 1010 01 1010 01 1010 00 1010 00 3(112 3(112 0(00)2 3(112 0(002 3(112 0(00)2 Hit Hit Miss Miss Hit Miss Miss 1010 0011 0010 0xA32 0xA3F OxA40 0xA70 OxA4D 0xA30 0xAOF 1010 0100 0000 1010 0111 0000 1010 0100 1101 1010 0011 0000 1010 0000 1111 3) Consider the access sequence from 2) and draw the state of the cache at the end of that sequence, filling out the table below. In the data column state which data is found at that entry (e.g. Mem[OxA30]). (4 Points) Index valid Tag Data