Consider a 5 stage pipeline (IF ID EX MEM WB), where each stage takes exactly 1 cycle. The pipeline is initially empty. Ignore any structural hazards. There is no branch prediction; you fetch the next PC, and flush the pipeline ater if needed. The ISA follows opcode dst, src1, src2 format. We have the following instruction stream Target: I.W R 0(R2) SUB R4 R4 R1 ADD R4 R3 R2 ADD R5 R3 R4 SUB R2 R2 1 BNEQ R2 0 Target Branch if not equal to AND R5 R3 R1 It turns out that the branch is not taken. Draw the pipeline timeline diagram in the absence of any data forwarding until the last instruction (AND) is retired. Use the same convention as the PIPE-8 slide. Assume that each cycle, register writes happen before register reads in ID. Consider a 5 stage pipeline (IF ID EX MEM WB), where each stage takes exactly 1 cycle. The pipeline is initially empty. Ignore any structural hazards. There is no branch prediction; you fetch the next PC, and flush the pipeline ater if needed. The ISA follows opcode dst, src1, src2 format. We have the following instruction stream Target: I.W R 0(R2) SUB R4 R4 R1 ADD R4 R3 R2 ADD R5 R3 R4 SUB R2 R2 1 BNEQ R2 0 Target Branch if not equal to AND R5 R3 R1 It turns out that the branch is not taken. Draw the pipeline timeline diagram in the absence of any data forwarding until the last instruction (AND) is retired. Use the same convention as the PIPE-8 slide. Assume that each cycle, register writes happen before register reads in ID