Consider a 5 staged pipelined MIPS processor where its operation is divided into 5 stages. Each stage is timed as shown below. What is the clock period of this processor, Execution Time Stage: Fetch Decode Execute Memory Write Back Time: 116 ns 179 ns 254ns 81 ns 231 ns a. 254.00 ns b. 81.00 ns c. 861.00 ns d. 172.20 ns e. None of the options